In systems, such as communication systems, circuit cards are often required to be replaced without impacting the normal system functionality. Typically, such cards are replaced while the other parts of system continue to receive their full power supply. Because of this requirement, input/output (I/O) pads of integrated circuits or chips included on these cards can have a signal on their pads even when these chips are not receiving their own power supply. This situation is commonly referred to as a “hot-plug” where the chip would be referred to as “hot-pluggable.” For this capability, the chip input receivers (i.e., buffers) must have hot-plug capability. In internal circuit protection terms, the critical current paths should be switched off to accommodate the “live insertion” of a chip into a system where the chip power supply is not yet at its full level, but where a signal may be present at a chip pad.
Because chip technologies are improving by shrinking dimensions to allow for continued performance enhancements, board power supplies typically remain at least one generation behind. Thus, the I/Os inside the chips may be driven using a higher power supply, so both input and output may also see the higher supply voltage. As recognized by the present inventors, such I/Os may need to be protected from supply “over-voltage” conditions where the I/O is essentially supplied by a higher voltage level than the fabrication or core technology used to implement the transistors in the I/O circuitry. Over-voltage protection, in circuit implementation terms, includes, for example, situations where the VGS (transistor gate-to-source voltage), VDS (transistor drain-to-source voltage), and VGD (transistor gate-to-drain voltage) differences across any associated transistor should not be allowed to face more than a designated value, such as 2.75 volts for a given transistor technology. If each such transistor is protected, then the I/O circuit as a whole can be protected.
A conventional approach to implement the hot-plug capability is shown in circuit 20 of FIG. 1. There are two basic modes of operation: a “live insertion” mode (e.g., the “hot plug” situation) and a “normal” mode. In the live insertion mode, the NGATE node 22 is at a voltage level of about PAD-2Vt (i.e., about two transistor threshold voltages below the voltage level applied to the PAD node 24) and the PGATE node 26 is essentially the same voltage level as the NGATE 22. Thus, virtually no current path exists through transistor MP1. In the live insertion mode, the circuit 20 may tolerate up to about 3.6 volts at the PAD 24. In the normal mode of operation, the PGATE node 26 will be about 2Vt (i.e., about two transistor threshold voltages) above the ground level, this will turn on transistor MP1, and NGATE 22 will be around the VDD level. Thus, the PAD signal 24 will be substantially passed to the core 28 by transistor MN1.
This conventional approach of FIG. 1 has two main disadvantages. First, this circuit 20 cannot take care of over-voltage if the chip power supply is greater than the technology supports, so there is no effective over-voltage protection. For example, if VDD is about 3.6 volts in normal operating conditions and PAD 24 is about 0 volts, MN1 is subjected to an over-voltage condition. Second, the signal passed to the core does not provide a rail-to-rail output and this adversely affects the Vih (minimum input level detectable as a logic high) and Vil (maximum input level detectable as a logic low) levels.
As recognized by the present inventors, what is needed is an input buffer having over-voltage tolerance and hot-plug capability, and if desired, also providing a full rail-to-rail output to the associated chip core. It is against this background that embodiments of the present invention have been developed.